In the design of communication chips, in order to meet the needs of the rapid increase of the speed and capacity of communication networks, the pipeline structure processing has been adopted in more and more chips. The pipeline technology is a technology of having the parallelism with space and time in computer technology, which breaks down one sequence process into several sub-processing steps, each of which can effectively perform simultaneously on the special independent module. These sub-processing steps are called stages, while every pipeline stage is composed of current register and hardware processing module (pure logic circuit), the former providing input to the latter, and the output of the latter point to the current register of the next stage; under the effect of clock pulse, every stage transmit the result from the completed processing to the next stage simultaneously. Submitting the command to the pipeline promptly, so as to assure that the command is continuously flowing in the pipeline, is the key of obtaining highly effective pipeline.
FIG. 1 illustrates the command submitting method of ring-form pipeline in the prior art, the ordinate stands for the stage of the pipeline, including six stages of pipelines, while the abscissa stands for time. A, B, C, D, E, F and G stand for the commands performed. The inserting position of the command is the first stage, and the command exiting position is the third stage of the pipeline. In case that all the pipeline stages are full, A, B, C, D, E and F are all performing in the pipeline, each of the current inset processing units inserts new command only after the pipeline commands entirely exit the cycle pipeline, as is illustrated by the figure, the new Command G is inserted after Command A completely exits the cycle pipeline, the “bubble” appears from the fourth stage to the sixth stage of the pipeline. Therefore, it cannot be guaranteed that the pipeline is flowing continuously, which thus affects the utilization efficiency of each elements of the pipeline and the parallelism of the command performance.